1. Field of the Invention
The invention relates to the field of high density MOS memory arrays.
2. Prior Art
It is generally recognized in the fabrication of integrated circuit MOS memories that yields are not substantially affected by device densities. Thus, one method of producing more economical memories is to increase device density such that for a given size substrate more storage is provided. However, certain prior art circuits and designs require substantial substrate area, and do not lend themselves to high density memory arrays.
In the prior art, particularly in dynamic random-access memories (RAMs), sense amplifiers disposed along each bit line in an array are commonly utilized. Often these sense amplifiers comprise bistable circuits which couple the bit sense line to a source of potential (power supply) through load transistors. Also in these memories pull-up transistors or networks are used to precharge the bit sense lines during a read cycle. By way of example, using prior art circuits in a 16K array having 128 bit sense lines bisected by a sense amplifier, 260 relatively large devices are required to pull-up or precharge the bit sense lines. As will be seen, the present invention eliminates the pull-up transistors and precharges the bit sense lines through the load transistors of the sense amplifiers.
Noise suppression techniques are known in the prior art for suppressing noise on word lines in a memory array. For example, latch circuits are used on word lines to suppress noise. In "An 8k b Random-Access Memory Chip Using the One-Device FET Cell", by Hoffman and Kalter, The Journal of Solid-State Circuits, Vol. SC-8, No. 5, October 1973, at page 301, a three-device latch circuit is shown for use on each half word line in an array. Again a large number of devices are required to provide noise suppression, hence limiting the number of bits of storage possible for a given substrate area. As will be seen, the present invention provides noise suppression for the entire array with two devices.